Complexity Effective ASIP Architectures for Network Processing and Multimedia Acceleration
نویسنده
چکیده
xiii 1 Processor Design 1 1.1 Technology Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Application Trends . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.3 Choice of Implementation Platforms . . . . . . . . . . . . . . . . . . . . . . 7 1.4 ASIP Design Methodologies . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.5 Complexity Effective Design . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2 Processor Architectures: A Complexity Perspective 15 2.1 Instruction Level Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.1.1 Superscalar Processors . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.1.2 VLIW Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 2.2 Task Level Parallelism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
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تاریخ انتشار 2003